The present invention relates to semiconductor devices. Particularly, this invention relates to non-volatile semiconductor memories having ferroelectric capacitors, and methods of fabricating such non-volatile semiconductor memories.
Ferroelectric memory cells having a ferroelectric thin film have been developed for highly reliable non-volatile semiconductor memories with low power consumption.
Such a non-volatile semiconductor memory is described with respect to FIG. 25.
A silicon oxide Film (SiO.sub.2) 102 is formed on a semiconductor substrate 101 for shallow trench isolation. A gate electrode 104 is formed on the substrate 101 via another SiO.sub.2 106. The gate electrode 104 is covered with an insulating film 109 and a side-wall insulating film 108 at its top and side faces, respectively. The films 108 and 109 are made of Si.sub.3 N.sub.4 or SiO.sub.2, etc.
The substrate 101 is doped with impurities by ion implantation to form an impurity diffusion layer 103 at a shallow depth of 0.1 .mu.m for fabricating a transistor Tr.
A mid-layer insulating film 105 is deposited over the substrate 1 and flattened by chemical mechanical polishing (CMP). A contact hole (window) 161 is formed in the film 105. The hole 161 is filled with a tungsten film 107 by blanket chemical vapor deposition (CVD). The tungsten film overflowed the hole 161 is removed by CMP. Formed between the inner wall of the hole 161 and the film 107 is a barrier metal layer of Ti/TiN.
Formed over the mid-layer insulating film 105 is an insulating film (Si.sub.3 N.sub.4) 110 which will be the base layer of a capacitor. A lower electrode 191, a ferroelectric film 192 and an upper electrode 193 are deposited in order on the insulating film 110 as capacitor layers. The capacitor layers are processed into a shape shown in FIG. 25 by reactive ion etching (RIE).
A mid-layer insulating film (SiO.sub.2) 111 is deposited over the insulating film 110 to cover the capacitor layers. Contact holes (window) 163 and 164 are formed in the film 111 and filled with tungsten films 162 by blanket CVD. The tungsten films overflowed the holes 163 and 164 are removed by CMP.
The contact hole 163 is formed on the contact hole 161 so that the tungsten films 107 and 162 are electrically connected to each other. The contact hole 164 is formed on the upper electrode 193 so that the tungsten film 162 in the hole 164 is electrically connected to the upper electrode 193. A barrier metal layer of Ti/TiN is also formed between the inner wall of the holes 163 and 164 and the film 162.
An electrode 112 of aluminum for wiring is formed on the mid-layer insulating film 111 by patterning. The electrode 112 is electrically connected to the tungsten films 162 in the contact holes 163 and 164 so that the upper electrode 193 of the capacitor is electrically connected to the impurity diffusion layer 103.
The capacitor and transistor pair formed as described above is used for ferroelectric random access memories (FRAMs). Such a semiconductor memory mostly has an array of memory cells each having two capacitors and two transistors.
As shown in FIG. 25, the gate electrode 104 functions as a word line (WL). Tungsten films 107a and 162a buried in contact holes 161a and 163a, respectively, are connected to an electrode 112a which is then connected to a bit line (BL).
Ferroelectric memory cells as described above are disadvantageous in that at least three contact holes 161, 163 and 164 are required to form electrical connection between the semiconductor substrate 101 and the upper electrode 193. Each contact hole requires photolithography and reactive ion etching (RIE) processes due to difference in depth.
The contact hole 163 and the three layers 191, 192 and 193 of the capacitor must be separated from each other to avoid short-circuit which would occur due to their mis-arrangement in photolithography. This results in a large space for each memory cell on a semiconductor substrate to retard device miniaturization.
Ferroelectric capacitors which are extremely thicker than usual capacitors give a very large aspect ratio of the diameter to depth of the contact hole 163. Such an aspect ratio degrates electrical conducting through the contact hole 163. This also retards device miniaturization, and does not meet the demands for mobile communications using, such as, non-contact identity cards.